1. Field of Invention
This invention is related to testing semiconductor memories and in particular testing very high speed memories.
2. Description of Related Art
The speed of today's computers places demands on the speed of memory chips to keep pace. As the memory chips get faster the ability to test them becomes more difficult and costly to develop new and faster testers. This is compounded by needing to probe the memory chips while still in a wafer form so that they can be sorted for performance. The impedance characteristics of the probes places additional limitations on the ability to test fast memory chips.
In U.S. Pat. No. 5,831,918 (Merritt et al.) an on chip timing circuit has an oscillator which is controlled by a test key that varies the frequency of the oscillator. This test circuit is used in stress testing a DRAM. In U.S. Pat. No. 5,457,400 (Ahmad et al.) an internal test circuit is provided with an additional conductive layer to power the test circuit. The test circuit is used to test DRAM's and other memory devices at the wafer level. In U.S. Pat. No. 4,890,270 (Griffith) a circuit is contained on a chip to determine the speed at which the particular chip operates. An external clock provides a bench mark against which to compare the operations of the chip can be compared.
In order to perform a performance test at the wafer level on high speed memory chips, fast testers and improved probes are required to apply high speed signals and detect the test results. This places a strain on resources to constantly keep up with the evolution of high speed memory chips. A means is needed that allows the memory chips to be tested for functional performance prior to sorting at the wafer level. Being able to do this improves through put, yield and reduces testing at higher package levels.